Here is a summary of the technical writers and people who provide other technical services for clients. Click a name for the writer's background.
Forrest Warthman is the founder of Warthman Associates, and he continues to lead writing projects as a principal writer, editor, and project manager. He has personally written many of the documents listed on the projects page.
In addition to writing, Forrest has designed and led the development of six hardware and software prototypes, including a prototype for a flat-panel handwriting and drawing device, a cost-accounting application marketed in cooperation with Microsoft, a file-conversion application for the IBM DisplayWriter, two audio synthesizers based on Intel neural-network chips, and several Java animations.
Forrest received an M.A. in Architecture and an M.A. in City Planning from the University of California at Berkeley. His city-planning thesis on urban telecommunication networks was written under the chairman of the Electrical Engineering and Computer Science Department. His architecture thesis on transportation networks was written under the chairman of the Transportation Engineering Department. He received his B.S. in Design from the University of Michigan.
Forrest gave a presentation on Cities and Computers: Their Architecture at Stanford University and UC Berkeley. The presentation describes computer functions that work like city functions. The video is at: Cities and Computers Video
John Goetz has had a 23-year career at IBM as a microprocessor and computer-system architect, product marketing manager, verification-tool developer, and logic designer. He has written technical manuals and engineering specifications throughout his career, including documents about the Cell Broadband Engine (CBE), PowerPC, x86, and MIPS processor architectures, network processors, and reconfigurable logic. At Warthman Associates, John has written technical documents for AMD, PMC-Sierra, and Xilinx about the x86, PowerPC, and MIPS processor architectures, and for Infineon about industrial semiconductors.
Prior to Warthman Associates, John was at IBM for 23 years, most recently as a senior engineer in IBM's Global Engineering Solutions (GES) architecture group, where he architected embedded imaging solutions based on the Cell multiprocessor and ASICs for the aerospace, defense and health care industries, including CT, PET, MR, and ultrasound technologies. Before that, he taught high-school mathematics and wrote standard specifications for the RapidIO Trade Association. He was a senior engineer and marketing manager for IBM's Network Processor Business Line, where he defined new PowerPC-based products and positioned existing products for network applications. Before that he was a senior processor architect working on product strategy of system-on-chip (SoC) PowerPC products and x86 business relationships. He architected and led the verification of an operating mode for the PowerPC 615 processor that executed multiple instruction sets, and he served as the in-house consultant to IBM design and verification teams on all issues related to PowerPC and x86 instruction-set architectures. He was the principal editor of the engineering specification for the PowerPC 615 processor. Prior to that he managed the department responsible for IBM’s x86 processor architectures and verification. He began his career at IBM in electronic design automation (EDA), responsible for developing simulation and logic-synthesis tools.
He has five patents in areas including microprocessor cache design, multiple-instruction-set support, and logic-network optimization.
John received his B. S. in Electrical Engineering from University of Notre Dame, followed by masters coursework in microprocessor architecture and operations research at the University of Vermont.
Thomas Sidle has broad experience developing, using, and managing the development of electronic design automation (EDA) tools for digital design and fabrication of computer systems, ASICs, FPGAs and other semiconductor devices. He has designed architectures, managed product development, and written code for more than twenty EDA tools. Along with this work he has written dozens of documents, including architecture specifications, marketing plans, implementation and coding plans, user references, and marketing collateral.
Prior to joining Warthman Associates, he was VP of advanced CAD technology research and director of advanced CAD development at Fujitsu Laboratories in California. In these roles he defined user requirements, specified technical architecture, and managed development of many EDA tools, including tools for logic synthesis, clock-tree synthesis, timing analysis, formal verification, logic-equivalence checking, design-for-manufacturing, UML-based electronic system-level design tools for hardware/software co-design. At Amdahl, he was principal marketing manager for telecom products and programs, principal product manager for corporate marketing, principal computer architect and planner, and manager of advanced design-automation development. During this time he developed products combining Sun SPARC servers with S/390 systems for data centers, led product-strategy development for UNIX mainframes, managed UTS UNIX and OS-enabling products, managed vendor relationships and the UTS UNIX third-party porting lab, formed the VLSI design-tools development department, developed the architecture for new mainframe EDA tools, promoted high-level design methods using VHDL and logic synthesis, developed a cycle simulator and system-verification methods for mixed-signal systems, and developed tools for design-rule checking, logic-synthesis, and timing analysis. Prior to that he was a technical staff member at Scientific Calculations, a project engineer at National Advanced Systems, and an engineering programmer at Burroughs. He holds one patent on invariant checking and is co-author of four other patent applications.
Thomas received his B.S. in Electrical Engineering and Computer Science from the University of California at Berkeley, and his M.S. in Computer Science from the University of California at San Diego.
Mr. K.D. Smith has a long and distinguished career designing and developing digital and analog electronic circuits and systems, teaching electrical engineering, and authoring technical publications. He has written about system-on-chip products, Internet and LAN chips, DSPs, workstations, peripherals, ASICs, medical devices, test devices, and measurement systems.
Prior to joining Warthman Associates he worked at Hewlett Packard, where he led the electronic design and development of the FireHawk workstation and a SCSI disk controller for an Internet server, including the architecture, system, logic, circuit and board design, bread-boarding, test-software modifications, and analog and digital testing. At the U.S. Air Force he led the design and development of F16 and F4 aircraft weapons systems using Xilinx FPGAs and VHDL tools. He was a senior scientist at Jet Propulsion Lab (JPL), where he designed the logic and layout of a GaAs chip used to verify DSP devices, and he performed architectural, logic, and circuit analyses of microprocessors for deep-space in-flight diagnostics using a scanning electron microscope. At the University of Utah, he designed analog CMOS cells for a mixed-signal simulator, and he designed an artificial-heart control system using embedded controllers, ASICs, and analog devices. He also taught undergraduate and graduate electrical engineering and computer science courses, for which he received the University's Outstanding Electrical Engineering Teaching Award, and he served on the EE/CS curriculum committee for establishment of a Computer Engineering degree. Prior to that he worked at American Micro Systems and National Semiconductor, where he designed custom and standard-cell chips for LAN control, disk control, satellite-TV descrambling, high-speed graphics, CRT control, medical-device control, and IC testing.
He has published refereed journal articles, conference papers, and company publications on many of his research and development projects, including his LAN chipset, artificial heart control, and VLSI testers. He authored two textbooks, the JPL/NASA ASIC Guide and General Instrument's MOS LSI Design. He holds two patents on IC-test and microcomputer design.
K.D. received his B. S. and M. S. in Electrical Engineering from Utah State University, followed by Ph.D. coursework in electrical engineering at Stanford University and the University of Utah
Margi Ference is an electrical and software engineer, and a versatile writer and editor. She has written technical manuals about reconfigurable processors, system-on-chip Internet-appliance processors, 3D graphics software, chip design and simulation, chip packaging processes, and chip layout software. She has programmed online help functions and tools for VLSI design and manufacture.
Prior to joining Warthman Associates, she worked as a technical writer and programmer at IC Editors, a developer of IC layout and design-rule verification software, where she wrote manuals about general-purpose VLSI layout products and programmed add-ons to the layout software in C++ and a macro language. At FastSURF, a developer of 3D surface-modeling software for defining spline and curves surfaces, she wrote manuals about the surfacing CAD software and programmed online help functions. Prior to that she worked at IBM for eight years as a software engineer. Her responsibilities included the development of software for custom VLSI chip design and manufacturing, including design and programming of a CAD and simulation environment running on workstations and hardware simulators. She wrote code in C and C++, using object-oriented programming concepts. She also documented the software tools she developed and trained users within IBM. She provided programming support for VLSI design synthesis on an IBM/VM operating system, and she had overall responsibility for computer verification of physical design data for custom VLSI parts in an IBM/MVS environment. She created several sets of design documentation for VLSI designs, and she wrote programs to automate many tasks in an IBM VLSI testing laboratory.
Margi received her B.S. in Electrical Engineering from Rice University. In addition to her professional accomplishments, she is the mother of two children.
Dan Solis is an expert C and C++ programmer. His broad programming experience ranges from applications to systems-software development on Windows, Unix, handheld, and real-time platforms. He has designed and coded object-oriented and conventional programs for database, finance, supply-chain management, graphical user interface, satellite tracking, and training applications. He has also written compilers, decompilers, and operating-system services. He is a Microsoft Certified Systems Engineer (MCSE), and has developed and taught training seminars in object-oriented programming and system administration. His 2006 book, Illustrated C# 2005, presents the C# programming language in a unique visual way.
Prior to joining Warthman Associates, Dan developed software for a U.S. Air Force satellite tracking and information system at Lockheed Martin, coded a supply-chain management product and graphical user interface for PeopleSoft, converted a mainframe database system to a three-tiered business-object architecture at American Student Assistance, and developed commercial-airline mail-routing software for the U.S. Postal Service. At Microsoft Consulting Services, he implemented groupware using Microsoft Exchange Server. At Fidelity Investments, he co-developed the object architecture for a retirement-portfolio planning system and a graphical user interface for a financial instruments reporting system used by fund managers. He also helped develop a Fidelity financial-calendar system used by trading programs, porting the software to Windows NT as a DLL. He was one of the major architects at Computervision for a bill-of-materials application, producing the object-oriented analysis and design, as well as coding a prototype and documenting the design. For four years, he developed and taught technical training seminars and workshops in the U.S. and Europe on C and C++ programming, object-oriented analysis and design, and Unix and Windows tools and system administration. He was a software engineer at DEC, GenRad, and Hughes Aircraft, where he developed database, compiler, and real-time process-control software.
He has programmed in Visual C++ with Microsoft Foundation Classes (MFC) for Windows and PocketPC, Microsoft SQL Server, WIN32 API, Unix, and Linux software environments.
Dan received his Master’s degree in Computer Science at the University of California at Santa Barbara. He received his Bachelor’s degree in English and Biology at Westmont College. For his master’s thesis, he developed a symbolic executor-compiler for Pascal that cross-compiled Pascal source code into Lisp.
Martin Morf is a content consultant to Warthman Associates' writers. He is an expert in the theory of information, control, estimation, and computer architecture. He is active in research on smart photonic networks, parallel and adaptive computing, specialized coprocessors (fluid-flow, communications, real-time control, and DSP), micro-MRI informatics, brain imaging, electro-optical and quantum devices, sub-nanosecond arithmetic processing, and information-preserving transformations. He has participated in a wide variety of research projects, most recently in projects that bring together the disciplines of biology, information technology, microelectronics, and physics.
He has been Visiting Professor of Electrical Engineering at Stanford University, Co-Director of the Stanford Computer Architecture and Arithmetic Group, Professor of Computer Science at ETH Zurich, Professor of Electrical Engineering and Computer Science at Yale University, and Visiting Professor at several institutions including NASA/Ames Research Center, Stanford University's Center for Integrated Systems, Xerox PARC, IBM T.J. Watson Research Center, and ETH Zurich's Institute for Control, Institute for Biomedical Engineering, and Institute for Mathematics. He has also conducted research projects for Canon Research America, Xerox PARC, RCA, and Chevron Research. Early in his career, he served in the Swiss Army Signal Corps.
He has authored or co-authored over 250 publications, including recent publications on reconfigurable and adaptive computing, photonic modulation and routing, computing-system optimization, estimation theory, nanotechnology architectures, and speech modeling.
Martin received his Federal Diploma in Electrical Engineering at ETH Zurich, and his M.S. and Ph.D. in Electrical Engineering at Stanford University. He also received an honorary M.A. from Yale University.