Microprocessor Signal Timing

The following writing example describes an inquire operation (also known as a snoop operation) involving three hypothetical chips: a microprocessor (called the processor), a system controller (called the controller), and another bus master (called the local-bus master).

The example is written for an audience of computer-system hardware developers.

Inquire-Cycle Timing

Inquire operations are initiated by the controller whenever another bus master attempts to access memory that is shared by that bus master and the processor. The operations are a means of enforcing coherence between the contents of the shared memory and the processor's on-chip cache, so that any device having access to the shared memory is assured of reading the same information as any other device reading the same address.

An inquire operation causes the processor to determine whether it has copied the contents of a memory address into its cache and, if so, whether it has modified the value of its copy. The memory address for the inquire operation is the one which the other bus master is attempting to read or write.

The three chips and shared memory are connected by three buses, as follows:

• Processor Bus: This bus is shared by the processor and the controller. It carries the following signals; a # symbol appended to the signal name indicates an active-low signal:
  • PGRNT# is processor grant.
  • CALE is controller address validation.
  • ADDR[31:2] is processor address.
  • ALE# is processor address validation.
  • D[63:0] is processor data.
  • HITM# is inquire hit modified.
  • PACK# is processor acknowledge.
  • CACK is controller acknowledge.
• Local Bus: This bus is shared by the controller and the local-bus master. It carries the following signals:
  • LREQ# is local-bus-master request.
  • LGRNT# is local-bus-master grant.
  • LADDR[31:2] is local-bus-master address.
  • LADS# is local-bus-master address validation.
  • LD[63:0] is local-bus-master data.
  • LRDY# is local-bus-master ready.
• Memory Bus: This bus is shared by the controller and memory, but none of its signals are shown in the timing diagram.

The timing diagram below shows an inquire operation hitting a modified location in the processor's cache, followed by a writeback, from the processor's cache to shared memory, of the modified data, followed by a memory access to that address by the local-bus master.

In the clock-by-clock sequence described below, a signal is said to be asserted or negated in the clock in which other devices sharing the bus can validly sample it asserted or negated, on a rising edge of a clock. Thus, if the processor is said to "assert ADS# in clock 2" the processor actually begins driving the signal Low in the latter part of clock 1, so that it is ready to be sampled Active Low on the rising edge of clock 2.

The clock-by-clock sequence is:

In the first clock, the local-bus master asserts LREQ# to request mastery of the system's address and data buses. The controller responds by negating PGRNT# in the next clock, causing the processor to release the bus, and asserting LGRNT# in the following clock, thereby granting the buses to the local-bus master. One clock later, the local-bus master drives its memory-access address on LADDR[31:2] and validates it by asserting LADS#.

Two clocks after the assertion of LADS#, the controller initiates an inquire operation to the processor by asserting CALE and echoing the local-bus master's read address on ADDR[31:2]. The processor asserts HITM# in the next clock and, one clock later, asserts PACK# to validate HITM#. The controller responds in the next clock by asserting CACK.

Two clocks later, the processor drives the inquire address on ADDR[31:2] (the same address that it received from the controller) and asserts ALE# to validate the address. The controller asserts PGRNT# in the same clock as ALE#, and it asserts CACK in the following clock. One clock after the assertion of CACK, the processor begins writing back four quadwords (the complete 32-byte cache line containing the modified data) on D[63:0].

In the clock after the processor writes back the last quadword of data, the controller copies the required doubleword onto LD[31:0] and negates CACK. The local-bus master asserts LRDY# to after it has read the data LD[31:0], and one clock later it negates LREQ#. In the next clock, the controller negates LGRNT# to terminate the operation and asserts PGRNT#, returning bus mastership to the processor.