Technical Writing Examples

Multicore Processors

Sony, Toshiba, IBM's (STI's) Cell Broadband Engine Programming Handbook. A 900-page book describing all aspects of programming for the nine heterogeneous cores on the Cell Processor chip.

Adapteva's Epiphany Architecture Reference Manual describes a low-power multicore parallel computing fabric that connects cores in a low-latency mesh network-on-chip (NoC).

Plurality's HyperCore Software Developer's Handbook describes a fine-grained, task-oriented programming model for parallel applications managed by a hardware synchronizer and scheduler.

Networking and Internet Protocols

The Delay-Tolerant Networks Tutorial, written for the Internet Research Task Force (IRTF), describes the architecture of a mobile Internet protocol for Earth and outer-space.

IBM's PowerEN PCIe Card User Manual describes a card that uses an IBM PowerEN processor to monitor high-volume packet traffic in edge-of-network routers.

The PMC-Sierra RM9000x2 Integrated Multiprocessor User Manual describes a MIPS multiprocessor system-on-chip (SoC) for control- and data-plane network routing.

Myricom's Datagram Bypass Layer (DBL) User Guide describes their software for accelerating enterprise applications whose performance depends on user datagram protocol (UDP) latency.

Application Programming Interfaces (APIs)

The Multicore Association's Multicore Communications API (MCAPI) Specification defines an API for communication and synchronization between multiple processing cores.

Orbcomm's Machine-to-Machine (M2M) Provisioning Portal Developer API Specification describes their web services description language (WSDL) interface that supports satellite and cellular-network asset tracking.

Zircon's Installation Guide for UNIX Platforms is for a middleware API that maps mission-critical applications to a pool of heterogeneous hardware and OS platforms.

Our own Java API for network animation, such as these animations on our web site.

International Standards

The Mobile Industry Processor Interface (MIPI) Alliance's Specification for Unified Protocol (UniPro), one of several mobile-device standards that we edited over the past 7 years with the IEEE-ISTO standards organization.

The Linux Mobile (LiMo) Foundation's Software Architecture Document, one of several Linux-based mobile-device standards that we edited in cooperation with the IEEE-ISTO.

Graphics Processors

The AMD/ATI R600-Family Instructions Set Architecture Manual describes the instructions for high-performance graphics processing units (GPUs).

The AMD/ATI Compute Abstraction Layer (CAL) Intermediate Language (IL) Reference Manual describes the intermediate instructions used by GPU compilers.

The MicroDesign Resources (MDR) 3D Technology Report is an architectural research paper about a variety of 3D-graphics chips.

Media Processors

MicroUnity's BroadMX C/C++ Functions manual describes a 128-bit architecture that includes many vector instructions for media, such as convolutions on complex floating-point operands.

The PortalPlayer PP5001 Superintegration System-on-Chip Controller Databook describes the microarchitecture and programming of an SoC core for audio media.

x86 Processors

The AMD x86-64 Architecture Programmers Manual, 2,000+ pages that describe and illustrate their 64-bit x86 application- and system-programming instruction set.

NexGen's Nx586 Processor Databook describes their implementation of the x86 architecture. We also wrote their Nx686/Nx687 Processor Databook.

The original Intel486™ Microprocessor Family Programmer's Reference Manual. We also wrote Intel's i486 Hardware Reference Manual and several other Intel x86 manuals.

PowerPC Processors

IBM's PowerEN PCIe Card User Manual describes a card that uses an IBM PowerEN processor to monitor high-volume packet traffic in edge-of-network routers.

Sony's Guide to Cell/B.E. Programming Documentation for the Sony PlayStation 3, in which a PowerPC core manages eight SIMD cores. We also wrote the Cell Broadband Engine Programming Handbook.

IBM's PowerPC Compiler Writer's Guide describes how to write a compiler for microprocessors that run the PowerPC instruction set architecture (ISA).

IBM's PowerPC Tools catalog describes the system-software and hardware tools that support system development based on PowerPC microprocessors.

ARM Processors

The picoTurbo pT-100 Hardware Core Data Sheet describes technical details about this ARM-compatible processor core that is designed for systems-on-chip (SoCs).

LinkUp System's L7200SDB Standard Development System Hardware User's Manual describes a hardware development system for LinkUp's ARM-based L720x Internet system processor.

MIPS Processors

The MIPS-based Tensilica Instruction Set Architecture (ISA) Reference Manual. We also Tensilica's Verilog-like instruction-extension manuals and their GNU development-tool guides.

IDT's IDT79R5000 RISC Microprocessor Reference Manual describes the MIPS-architecture instruction set for this processor.

The MIPS Corporation Brochure gives an overview of the company's history, products, and markets.

SPARC Processors

We wrote three versions of the Fujitsu SPARClite MB8683x Data Sheet and SPARClite MB8683x User's Guide, which describe SPARClite embedded processors.

Fujitsu's SPARClite User's Guide describes this embedded processor's hardware microarchitecture and instruction-set architecture.

Processor Cores

The Xilinx Virtex-II Pro PPC405 User Manual describes a PowerPC processor core embedded in field-programmable gate array (FPGA) logic.

The picoTurbo pT-100 Hardware Core Data Sheet describes hardware details about this ARM-compatible processor core that is designed for use in systems-on-chip (SoCs).

Systems on Chip (SoCs)

The Synopsys Systems-on-Chip for High-Speed Communication Systems white paper describes design issues and solutions for ASIC-based SoCs used in broadband communications.

The PortalPlayer PP5001 Superintegration System-on-Chip Controller Databook describes the microarchitecture and programming of an SoC core for audio appliances.

The PMC-Sierra RM9000x2 Integrated Multiprocessor User Manual describes a MIPS-architecture multiprocessor SoC for control- and data-plane network routing.

Field-Programmable Gate Arrays (FPGAs)

Synopsys' FPGA-Based Prototyping Methodology Manual describes a systematic method for prototyping chips and boards using field-programmable gate array (FPGA) logic.

The Xilinx Virtex-II Pro PPC405 User Manual describes how to configure FPGA logic that surrounds an embedded PowerPC processor core.

Mixed-Signal and GPS Semiconductors

SiRF's GSD4t GPS Hardware and Software Databook describes a mixed-signal global positioning system (GPS) chip that is designed for use in cell phones and mobile navigation devices.

Ditrans' DT3824 JAZZ CDMA/AMPS Tri-Mode, Dual-Band Receiver Data Sheet describes a mixed-signal chip used in dual-band cell phones.

Tchip's IP1012 Global Positioning System (GPS) Receiver Baseband Data Sheet describes a baseband (non-modulated) receiver chip used in GPS devices.

Digital Signal Processors (DSPs)

Analog Devices' ADSP-2100 Family User's Manual describes the hardware architecture and instruction-set architecture of this family of DSP chips.

We wrote the original versions of Hitachi's SH-DSP 7410 Hardware Manual and SH-DSP Programming Manual.

Development Systems

Hitachi's D9000 Development System Hardware User Manual describes how to develop hardware and software in the Windows CE operating-system environment on their SH family of processors.

LinkUp System's L7200SDB Standard Development System Hardware User's Manual describes a hardware and software development system for devices using their ARM-based L720x Internet system processor.

Parallel Programming

Plurality's HyperCore Software Developer's Handbook describes a fine-grained, task-oriented programming model for parallel applications managed by a hardware synchronizer and scheduler.

This excerpt from the nCUBE 2 Supercomputers Parallel Programming Principles describes how to partition databases running on nCube parallel-processing supercomputers.

Adapteva's Epiphany Architecture Reference Manual describes the instruction set, pipeline, and onchip network for their multicore parallel-computing fabric.

Programming Languages

The nCUBE 2 Supercomputers Parallel Programming Principles manual describes the basic principles by which high-performance parallel programs can be created for nCube's supercomputers.

MageLang Institute's Java for C++ Programmer's Course Notes describes the similarities and differences between those two programming languages.

Nippon Telegraph & Telephone (NTT) LSI Labs' HSL-FX High-Level Description (HDL) User's Manual describes the grammar of their Verilog-like language for semiconductor design.

Electricity Networks and Loads

This Electric Reliability Council of Texas (ERCOT) Customer Move-Out State Transitions diagram defines building move-out scenarios. It is based on Karnaugh maps and written for Electronic Data Interchange (EDI) protocol programmers.

The Electric Power Research Institute (EPRI) User's Guide to the Over/Under Capacity Planning Model describes simulation and modeling systems for electric-power capacity planning.

The Energy Management Associates (EMA) PROMOD III Production Costing Model User's Manual describes methods for estimating the cost of electric-power production.

Biomedical and Biometric Devices

Nanosphere's Verigene Molecular Diagnostics System User’s Manual describes a laboratory system that processes and genotypes multiple genes in a DNA sample.

Nestor's Ni1000 Recognition Accelerator User's Guide describes the Ni1000 chip's real-time classification of patterns using artificial neural-network radial basis function (RBF) algorithms.

Industrial Products

Infineon's Hall-Effect Integrated Switches and Latches Application Note describes a magnetic-field-sensing microchip used in industrial and automotive applications.

Raychem's Chemelex Auto-Trace Pipeline Heating System Installation and Operations Manual describes a pipeline heating system used in chemical processing plants.

Semiconductor Processing and Test Equipment

Varian's 3190 Cassette-to-Cassette Sputtering System Operation Manual describes an electromechanical-chemical manufacturing machine for semiconductor chips.

KLA-Tencor's Alpha-Step 200 Data Sheet describes and illustrates the electromechanical properties and operation of this semiconductor test instrument.

Circuit-Design Tools

AT&T Bell Labs' SCHEMA User Guide shows chip designers how to create circuit descriptions from logic libraries using both a graphical user interface and a programming language.

Synergy Semiconductor's System Elements Design Handbook describes Synergy's high-speed emitter-coupled logic (ECL) circuit architecture and how to program its gate arrays.

The Xilinx Advanced CAD Technology (XACT) User's Manual describes the development system for this reconfigurable logic, including the computer-aided design (CAD) tools for implementing such logic.

Philips-Signetics' SNAP Design Manual describes the programming language used to configure their programmable logic devices.

Microprocessor Address Translation

We created this diagram for PowerPC microprocessors to show how addresses generated by programs (called "effective addresses") are translated into addresses that access memory (called "real addresses").

Pattern Recognition

This excerpt from Nestor's Ni1000 Recognition Accelerator User's Guide describes the chip's classifier and microcontroller hardware architecture. The chip was developed jointly by Intel and Nestor.

Register Organization

This diagram summarizes the fields and functions of Intel's Pentium™ Pro microprocessor internal control registers, with a text summary of each field.

Cache Coherency

The AMD-K5™ Technical Reference Manual describes the snooping function used in the processor's cache-coherency protocol.

Internet Ports

SRI International's ARPANET IMP Port Expander Technical Report describes one of the earliest implementations of the TCP/IP Internet protocols for routers.

Principles of Operation

Here is an excerpt from Nestor's Ni1000 Recognition Accelerator User's Guide that summarizes the methods by which the chip recognizes data patterns.

Data Sheets

IBM's PowerEN PCIe Card Data Sheet.

Ditrans' JAZZ Digital Receiver DT3824 For CDMA/AMPS Tri-Mode, Dual-Band Wireless Terminals Data Sheet.

Fujitsu's SPARClite MB86833 Embedded Processor Data Sheet.

Intel's 80170NX Electrically Trainable Neural Network Data Sheet.

Nestor's Ni1000 Recognition Accelerator Technical Specification.

KLA-Tencor's Alpha-Step 200 Data Sheet.

User Guides

Pretty Good Privacy's PGPmail 4.5 Quick Guide explains the installation, configuration, and day-to-day use of PGP's encryption program.

Writing Engineering Specifications

This series of slides, presented at a Design Automation Conference (DAC), illustrates and explains how to write maintainable engineering specifications using Microsoft Word and Adobe FrameMaker.

Visual Analogies

Forrest Warthman gave this presentation on Cities and Computers: Their Architecture at Stanford University and UC Berkeley. It describes computer functions that work like city functions. The video is at: Cities and Computers Video