Our technical writers write documentation about configurable embedded processors, including those with DSP and vector-processing architectures and those implemented as intellectual-property (IP) cores for applications such as communications systems and Internet appliances. This Tensilica data sheet describes a vector-instruction DSP pipeline architecture for their configurable processors.

• Length: 189 pages
• Audience: Embedded-system developers
• Service Performed: Original manuscript, editing, and camera-ready art