Bus-Signal Animation

The following Java™ applet animates the hardware signal timing used in various bus operations by microprocessors. Animation of signal timing has important advantages over conventional data-sheet timing diagrams:

  • Animations show which chips originate signals and which chips are the intended targets for the signals.
  • By providing richer visual information, in addition to conventional timing information, animations allow hardware designers to better "see" how signals interact.
  • Java animations are portable across platforms. Only a Web browser is needed.

After downloading, the applet appears (from top to bottom) as a block diagram of chips and interconnecting signals, a timing diagram detailing the transitions on each signal, and animation controls including buttons, speed scrollbar, and pull-down menu.

If the applet does not appear after several seconds, or if it continues to appear all gray, you may need to install Java on your computer, or you may be behind a corporate firewall that blocks incoming Java applets.

Press the Start button to begin the animation. You can adjust the animation speed with the scrollbar, stop the animation with the Stop button, or control the clock-by-clock sequence by repeatedly pressing the Step button. The pull-down menu selects one of three bus operations: a burst read from memory, two sequential burst reads from memory, or a cache-snoop hit. Further details are given below the image.

The block diagram shows six chips: four microprocessors (the stacked central processing units numbered CPU0, CPU1, CPU2, and CPU3), a system CONTROLLER that interfaces the microprocessors to memory, and a block of SDRAM (synchronous dynamic random access memory) chips.

The signals connecting the CPUs, controller and SDRAM are animated with the following colors:

  • GREEN (asserted, or for bus signals, valid)
  • RED (negated)
  • YELLOW (hi Z)
  • GRAY (invalid or don't care)

The timing diagram, below the block diagram, shows the clock moving from left to right. Each vertical dashed line represents a rising edge of the bus clock. Signals are sampled by the chips on rising edges of the clock.

The four CPUs share a set of bus-request signals (BREQ0# through BREQ3#) with which they arbitrate for bus mastership prior to driving bus operations. The small rectangles on the lower-left of each CPU represent this arbitration, which is also visible in the timing diagram. The winner of the arbitration pops to the top of the stack. (The arbitration relies on the fact that each BREQ# signal is connected to a different BR# pin on each Pentium III and Pentium Pro processor.)


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